VLIW processors exploit instruction-level parallelism (ILP) by issuing several operations per instruction to multiple functional units. In order to make the scheduling of operations tractable, all operations are assumed to be register-to-register. This places a lot of stress on the design of the processor datapath, which often centers around the design of register files that need to distribute a dozen or so operands each cycle to multiple functional units and accept multiple operands for writeback at various times. The processor datapath is comprised of functional units, register files, and the interconnect for carrying data back and forth between the register files and functional units. The functional units are responsible for executing operations supported in the processor's instruction format, while the register files store the source and destination operands of these operations.
A good design of a processor's datapath uses one or more multi-ported register files and a careful optimization of their read/write ports and interconnect datapath to the various functional units in order to maximize resource sharing and minimize cost.
Today, this design is conducted manually by designing a register-transfer level (RTL) model where the number and kinds of the functional units, the register files, and the topology of the datapath interconnect are decided by hand. This is a fairly cumbersome and error-prone process requiring hours of simulation and verification to achieve the desired functionality and to avoid unnecessary structural hazards. Traditionally, a small set of such designs (often 1) is created manually on the basis of simple qualitative analysis or a gut-feeling based on past experiences of the architect. The process of optimizing the number of read/write ports of the register files and orchestrating their usage by the various functional units at various times is also a very challenging and difficult task to be performed manually.